SPDIF Glitches
Re: SPDIF Glitches
digital information is sent in "packets" of data. the packets need to be put back together for playback. normally, it's a fairly linear stream, but...
Re: SPDIF Glitches
Its a synchronization thing... Time stamping embedded in the signal ensures slave is synchronized with master...
Otherwise the slave doesn't recognize digital boundaries. The digital receiver doesn't recognize what is audio data and what is clock data.
Like having two stopwatches, its next to impossible to have them in sync, unless something actually synchronizes them.
Spdif protocol uses embedded clock in signal in order to support multiple data rates, 44.1/48 etc.
Different bit depths are supported too - the standard supports up to 20-bit - 24-bit is a non standard extension.
The algorithm that embeds clock in audio data is called biphase mark code.
Otherwise the slave doesn't recognize digital boundaries. The digital receiver doesn't recognize what is audio data and what is clock data.
Like having two stopwatches, its next to impossible to have them in sync, unless something actually synchronizes them.
Spdif protocol uses embedded clock in signal in order to support multiple data rates, 44.1/48 etc.
Different bit depths are supported too - the standard supports up to 20-bit - 24-bit is a non standard extension.
The algorithm that embeds clock in audio data is called biphase mark code.
Not because it is easy, but because it is hard...
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Re: SPDIF Glitches
Would the ULLI settings also be a factor here?
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Re: SPDIF Glitches
Eanna wrote:Its a synchronization thing... Time stamping embedded in the signal ensures slave is synchronized with master...
Otherwise the slave doesn't recognize digital boundaries. The digital receiver doesn't recognize what is audio data and what is clock data.
Like having two stopwatches, its next to impossible to have them in sync, unless something actually synchronizes them.
Spdif protocol uses embedded clock in signal in order to support multiple data rates, 44.1/48 etc.
Different bit depths are supported too - the standard supports up to 20-bit - 24-bit is a non standard extension.
The algorithm that embeds clock in audio data is called biphase mark code.
xw8400
2.33 GHz Xeon Quad core (E5345 Socket 771) x2
32Gb ECC buffered memory
AMD HD7700
Samsung 850 EVO 250Gb root drive
Windows 7 Pro (64bit)
Sonar Platinum
XITE-1 (flipping awesome!)
2.33 GHz Xeon Quad core (E5345 Socket 771) x2
32Gb ECC buffered memory
AMD HD7700
Samsung 850 EVO 250Gb root drive
Windows 7 Pro (64bit)
Sonar Platinum
XITE-1 (flipping awesome!)
Re: SPDIF Glitches
happycritter wrote:Would the ULLI settings also be a factor here?
no.
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- Posts: 52
- Joined: Wed Oct 23, 2013 8:51 pm
Re: SPDIF Glitches
Thanks! Not trying to muddy the water, just wasn't sure what relations/dependencies existed w/ the hardware.garyb wrote:happycritter wrote:Would the ULLI settings also be a factor here?
no.
Cheers!
xw8400
2.33 GHz Xeon Quad core (E5345 Socket 771) x2
32Gb ECC buffered memory
AMD HD7700
Samsung 850 EVO 250Gb root drive
Windows 7 Pro (64bit)
Sonar Platinum
XITE-1 (flipping awesome!)
2.33 GHz Xeon Quad core (E5345 Socket 771) x2
32Gb ECC buffered memory
AMD HD7700
Samsung 850 EVO 250Gb root drive
Windows 7 Pro (64bit)
Sonar Platinum
XITE-1 (flipping awesome!)